1. Field of the Invention
The invention relates to a contact layout structure, and more particularly, to a contact layout structure positioned in a dense region.
2. Description of the Prior Art
Photolithography process has been an essential process in semiconductor manufacturing procedures. It includes steps of providing a photomask or photomasks having designed patterns such as circuit patterns, doped region patterns, or contact layout patterns and transferring said patterns to a photoresist formed on a substrate by an exposure step and a development step, thus those complicated patterns are obtained on the semiconductor chips precisely. After the photolithography process, implantations or etching processes are performed to construct those intricate circuit structures.
With a trend toward miniaturization of the semiconductor industry, and improvement in semiconductor manufacturing process, it is capable of forming both dense regions and iso regions on one chip. However, it is well-known that critical dimension (CD) of a layout pattern such as a contact layout pattern always faces an optical limit. In particular, an undesired condition that the opening merged in the dense regions is often found in after-development-inspection (ADI).
In addition, please refer to FIG. 1, which is a cross-sectional view of a conventional share contact opening. As shown in FIG. 1, a share contact opening 110 is positioned in a dense region such as a static random access memory (SRAM) region 102 of a substrate 100. The substrate 100 further includes a plurality of shallow trench isolations (STIs) 104 used to provide electrical isolation. The share contact opening 110 is formed in a dielectric layer 140 for forming a share contact (not shown) in following process. The share contact is used to electrically connect a source/drain 124, which is on an active region, of a transistor 120 and a gate 132 of another transistor 130, which is also formed on the active region, to an upper circuit layer. As shown in FIG. 1, because the share contact connects source/drain 124 and gate 132 of different transistor 120, 130, the share contact opening 110 is often made larger than conventional contact opening 112.
It is noteworthy that in the etching process used to form the contact opening, micro-loading effect caused by density difference between the dense region and the iso region often makes etch ratio in the dense region lower than that in the iso region. Furthermore, another problem is found in the dense region: because the share contact opening 110 is larger than the other contact opening 112, it is found that, in the same etching process, the conventional contact opening 112 has not been completely formed while the share contact opening 110 is well formed. In other words, when the conventional contact opening 112 is completely formed, the share contact opening 110 will be over-etched, even causing damage to the underneath transistor or the active region and thus adversely influences the yield. Those skilled in the art will easily conclude that although the share contact increases the utility rate of the valuable chip area, it simultaneously raises difficulty or complexity of the etching process control.
Therefore, a contact layout structure is needed to fundamentally avoid openings from the merging problem found in ADI and to avoid problems happening to process control as mentioned above.